A wide variety of integrated circuit memories are available for storing data. One type of memory is the dynamic random access memory (DRAM). A DRAM is designed to store data in a memory cell formed as a capacitor. Because charges on capacitors are dynamic, they must be refreshed periodically to store data. The period between refreshes increases as the initial charge increases. The data is stored in a binary format; a logical "one" is stored as a charge on the capacitor, and a logical "zero" is stored as a discharged capacitor. The typical DRAM is arranged in a plurality of addressable rows and columns. To access a memory cell, a row is first addressed so that all memory cells coupled with that row are available. After a row has been addressed, at least one column can be addressed to pinpoint at least one specific memory cell. The data stored in the memory cells is, therefore, accessible via the columns.
Every memory cell has an access transistor coupled to the memory cell for reading and writing data thereto. Because the memory cell is dynamic, the maximum available voltage should be used to write data to the cell to minimize the frequency of memory refresh cycles. In order to write the maximum voltage into the memory cell, the gate of the access transistor is driven to a pumped voltage level, Vccp. A set of global phase lines are used to connect the access transistors of an entire array to a Vccp voltage pump. Driving one of the global phase lines to Vccp requires excessive operating current. That is, only one row requires Vccp at any given time. The operating current can, therefore, be substantially reduced if only the portion of the global phase line connected to the addressed memory row were driven to Vccp.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an integrated memory circuit which provides fast row access times while reducing power consumption by driving local phase lines.